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Review of Case Materials
Reviews records, documents, testimony, data, and other relevant materials and consults with counsel regarding technical issues related to the matter.
Provide Expert Analysis
Applies specialized knowledge and experience to evaluate the technical or professional issues involved.
Form Expert Opinions
Develops independent, supportable opinions based on the available evidence and relevant standards.
Prepare Expert Reports
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An application-specific integrated circuit, or ASIC, is an integrated circuit designed for a particular application or defined set of functions rather than primarily for general-purpose use. An ASIC may combine custom logic with reusable elements such as memory, interfaces, or processor cores. Development can include hardware-description-language design, logic synthesis, physical implementation, timing and functional verification, fabrication, and post-silicon testing. Records from these stages can help determine whether a disputed problem is associated with the design specification, logical implementation, physical layout, fabrication, packaging, or operation of the completed device.
A setup-time violation occurs when data does not become stable early enough before the relevant clock edge, while a hold-time violation occurs when data does not remain stable long enough after that edge. Contributing factors may include logic and interconnect delay, clock skew and uncertainty, parasitic resistance and capacitance, supply voltage, temperature, semiconductor-process variation, crosstalk, and incorrect or incomplete timing constraints. Static timing analysis can evaluate timing paths before fabrication, while post-silicon measurements and testing can help determine whether observed device behavior is consistent with a timing-related problem under actual operating conditions.
Integrated-circuit designs are checked through multiple verification stages before fabrication. Functional verification may include simulation, formal verification, and equivalence checking, while static timing analysis evaluates whether relevant timing requirements are satisfied. After physical implementation, design-rule checking can determine whether the layout complies with fabrication rules, and layout-versus-schematic checking can confirm that the implemented connectivity corresponds to the intended circuit. Extracted parasitic information can also be used for timing, signal-integrity, power-integrity, and other signoff analyses before tape-out.
Prepares clear, well-supported expert reports outlining methodology, analysis, findings, and opinions.
Provide Deposition Testimony
Explains findings and opinions under oath and responds to questioning during deposition testimony.
Testify in Court
Presents specialized findings and opinions clearly to judges, juries, arbitrators, or other decision-makers.
Yes. A packaged integrated circuit can malfunction because of conditions outside the active circuitry on the semiconductor die. Possible sources include wire bonds, flip-chip bumps, package substrates, solder joints, connectors, power or ground delivery, package parasitics, thermal or mechanical stresses, and surrounding printed-circuit-board connections. Electrical testing, imaging, package inspection, interconnect analysis, and die-level measurements can help determine whether the failure originated in the die, package, board, or an interaction among them.
